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( doc no. hx8347 - d(t) - an ) HX8347-D(t) 240rgb x 320 dot, 262k color, with internal gram, tft mobile single chip driver preliminary version 01 september, 2008 http://www..net/ datasheet pdf - http://www..net/
-p.1- himax confidential sep, 2008 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. 1. mpu mode reference fpc circuit and initial code . ................................................... ............................. 4 1.1 cmo............................................ ................................................... ................................................... .. 5 1.1-1cmo 2.6reference fpc circuit ................. ................................................... ............................... 5 1.1-2 initial code for cmo 2.6 and 2.4 ........... ................................................... ................................. 6 1.1-3 cmo 2.0 2.2 2.4 2.8 reference fpc circuit ................................................... ......................11 1.1-4 initial code for cmo 2.0 .................... ................................................... ..................................... 12 1.1-5 initial code for cmo 2.2 .................... ................................................... ..................................... 17 1.1-6 initial code for cmo 2.8 .................... ................................................... ..................................... 22 1.1-7 initial code for cmo 2.4 .................... ................................................... ..................................... 27 1.1-8 initial code for cmo 2223 panel.............. ................................................... ................................ 32 1.1-9 initial code for cmo 2807 panel.............. ................................................... ................................ 37 1.2 cpt ............................................ ................................................... ................................................... . 42 1.2-1 cpt 2.0 reference fpc circuit............... ................................................... ............................... 42 1.2-2 initial code for cpt 2.0.................... ................................................... ....................................... 43 2. rgb mode reference fpc circuit .................. ................................................... ...................................... 48 2.1. initial code for reference .................... ................................................... ...................................... 49 3. otp programming ................................. ................................................... ................................................. 51 4. revision history ................................ ................................................... ................................................... .. 52 HX8347-D(t) 240rgb x 320 dot, 262k color, with internal gram, tft mobile single chip driver l ist of contents sep, 200 8 http://www..net/ datasheet pdf - http://www..net/
-p.2- himax confidential sep, 2008 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. figure 1. 1the HX8347-D mpu application reference c ircuit............................................. ........... 4 figure 2. 1 the HX8347-D spi+rgb application refere nce circuit........................................ ..... 48 HX8347-D(t) 240rgb x 320 dot, 262k color, with internal gram, tft mobile single chip driver l ist of figure sep, 2008 http://www..net/ datasheet pdf - http://www..net/
-p.3- himax confidential sep, 2008 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. table 3. 1 otp address mapping ..................... ................................................... ................... 51 HX8347-D(t) 240rgb x 220 dot, 262k color, with internal gram, tft mobile single chip driver list of table sep, 2008 http://www..net/ datasheet pdf - http://www..net/
-p.4- himax confidential sep, 2008 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. 1. mpu mode reference fpc circuit and initial code nreset nrd_e dnc_scl nwr_rnw 3. the input pin must be fixed iovcc or gnd when no use. refer to "pin description". ncs vcl ddvdh c31p vgl vgh c31n vreg1 vcom vcoml vcomh vddd te im0 im1 im2 osc dnc1 dnc vcom1 vcom ncs1 ncs vddd1 vddd nwr_scl1 nwr_scl vgh vtest1 vtest ddvdh1 ddvdh im3 im1 c08 c31n c31p im2 im2 vcomh1 vcomh u1 HX8347-D (bump up) vgl c11p vpp_otp hsync dotclk de nreset nrd_e nwr_rnw im3 im2 c22n ddvdh c22p g2 g4 g320 g1 g3 g317 g319 s1 s2 s3 s720 s719 s718 g6 g318 g315 g5 vgh c11n conn conn vcom ncs vssa dnc_scl vssc vci vssd vsync dummy27 dummy dummy23 dummy24 s262 s263 s361 s265 s266 s267 c21p c21n im0 sda d17 test10 d16 d15 test9 d14 d13 test8 d12 d11 test7 d10 d9 test6 d8 d7 test5 d6 d5 test4 d4 d3 test3 d2 d1 d0 test2 te cabc_pwm_out osc iovcc vddd c12p c12n c31p c31n vcl vreg1 vtest vmoni vcomh_dummy vcoml_dummy rcm1 rcm0 srgb smx smy ifsel vcom_dummy im1 test1 cabcpwmout im1 im3 c12p c02 (open) c12n te1 te vcoml1 vcoml vcl1 vcl nreset1 nreset vtest vgl1 vgl nreset iovcc nrd_e1 nrd vci nreset nrd vreg1 vreg1 nwr_scl vgh1 vgh gnd osc1 osc 240rgb x 320 tft panel im4 im0 im3 c21n c01 c21p c11p c11n vtest c10 1 - - 1 im3 im2 im1 8080 mcu 16-bits parallel type ii 0 0 im0 db8 db10 db9 db7 0 interface mode db12 db11 vddd 0 0 db13 db14 1 0 0 db15 iovcc 3-wire serial interface 8080 mcu 8-bits parallel type ii db17 db16 sda te 0 00 1 0 1 1 0 c22n c22p db1 db0 db4 db3 db2 0 1 - db6 db5 id 0 1 0 0 0 0 1 0 1 10 11 0 1 1 8080 mcu 9-bits parallel type ii c09 8080 mcu 16-bits parallel type i 8080 mcu 18-bits parallel type ii 8080 mcu 9-bits parallel type i vssa vssd im0 im1 im2 im3 gnd im2 im0 vci im1 4-wire serial interface 8080 mcu 8-bits parallel type i c06 vpp_otp c01 ( c11p/n ) c02 ( c12p/n )(optional) recommended spec. capacitor c04 ( c21p/n ) c03 ( ddvdh ) 1uf / 6.3volt. c06 ( vgh ) c05 ( c22p/n ) c09 ( vcl) c08 ( c31p/n ) c07 ( vgl ) 1uf / 10 volt. 1uf / 6.3volt. c10 ( vddd ) 1uf / 10 volt. 1uf / 10 volt. 1uf / 6.3 volt. 1uf / 16 volt. 1uf / 25 volt. 1uf / 6.3 volt. 1uf / 6.3 volt. 2. sdi pin is i/o pin. sdo is no use. conn1 conn1 conn1 vcoml vcomh sda cabcpwm db11 conn2 conn2 conn2 vssd vssa vssc db13 db15 ncs db5 db9 db8 db10 db14 db12 db7 db4 nwr_scl db3 db6 db0 db2 db1 dnc_scl nrd db16 gnd te db17 vreg1 c07 vgl vcl ddvdh conn1 conn2 cabcpwm vssc c03 c04 c21n c21p srgb="0" s1,s2,s3="b,g,r" c31p c12p c12n c31n smx="0" s720->s1 rcm[1:0]="0x" mpu i/f smy="0" g1->g320 cabcpwm pwm pwm vpp_otp vpp_otp1 vpp_otp ifsel="0" register-content interface dnc_scl c05 8080 mcu 18-bits paralle type i c22p ncs gnd1 gnd gnd2 gnd j1 fpc60-0.5-4.0l vci 1 vci 2 gnd 3 vcc 4 iovcc 5 nreset 6 db17 13 db16 14 db15 15 db14 16 db13 17 db12 18 db11 19 db10 20 db9 21 db8 22 db7 23 db6 24 db5 25 db4 26 db3 27 db2 28 db1 29 db0 30 nrd_e 31 nwr_rnw 32 dnc 33 ncs 34 flm 35 gnd 36 pwm_out 37 vsync 38 hsync 39 dotclk 40 enable 41 sdo 42 sdi 43 nc 44 nc 45 nc 46 nc 47 nc 48 nc 49 nc 50 nc 51 extc 52 dbs 53 im3 54 im2 55 im1 56 im0 57 gnd 58 bl+/nc 59 bl_gnd/nc 60 db23 7 db22 8 db21 9 db20 10 db19 11 db18 12 im3 1. vci, iovcc are separated from different power so urce to get better display quality. iovcc vci vci1 vci iovcc1 iovcc c22n figure 1. 1the HX8347-D mpu application reference c ircuit HX8347-D(t) 240rgb x 320 dot, 262k color, with internal gram, tft mobile single chip driver preliminary version 01 sep, 200 8 http://www..net/ datasheet pdf - http://www..net/
-p.5- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. 1.1 cmo 1.1-1cmo 2.6reference fpc circuit title size document number rev date: sheet of driver ic himax hx8347d a01 cmo 2.6" fpc rev a01 custom 1 1 friday , september 19, 2008 /cs rs vci c08 1u/10v notes 2 set ifsel="0" register-content interface mode. - vpp_otp 1 1 - c04 1u/10v notes 3 set im3~im0="1000" 80 system 18bit type i interface. notes 1 set iovcc=2.8v(1.65~3.3v);vci=2.8v(2.5~3.3v) iovcc c05 1u/10v vddd c10 1u/6.3v 0 vcom sda,scl,rs vpp_otp vpp_otp /cs db4 te db1 im3 te vcom im2 vcom iovcc vci vci db2 db3 db5 im2 im3 im0 im1 valid data bus interface 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 0 db17-10, db8-1 db7-0 db15-0 id - - 1 db17-10 sda,scl 00 0 00 1 10 1 1 1 1 db17-0 0 1 0 8080 mcu 18 bits parallel db17-9 db8-0 db17-0 vcl iovcc c09 1u/6.3v te j1 vci 1 vci 2 gnd 3 vcc 4 vcc 5 rest 6 db17 7 db16 8 db15 9 db14 10 db13 11 db12 12 db11 13 db10 14 db9 15 db8 16 db7 17 db6 18 db5 19 db4 20 db3 21 db2 22 db1 23 db0 24 rd 25 wr 26 rs 27 cs 28 flm 29 gnd 30 bl+ 31 bl- 32 db16 db13 db15 gnd db9 /reset db14 db12 db17 db11 /rd db7 db10 db6 db8 rs te gnd db0 /wr im0 im3 im0 im1 im2 db0 c03 1u/10v ddvdh 8080 mcu 18-bits parallel type ii 8080 mcu 16-bits parallel type i 8080 mcu 9-bits parallel type ii 3-wire serial interface 8080 mcu 8-bits parallel type ii 8080 mcu 16-bits parallel type ii 8080 mcu 18-bits paralle type i 8080 mcu 8-bits parallel type i 4-wire serial interface 8080 mcu 9-bits parallel type i c02 ( c12p/n )(optional) recommended spec. capacitor c01 ( c11p/n ) c07 ( vgl ) c06 ( vgh ) c05 ( c22p/n ) c04 ( c21p/n ) c03 ( ddvdh ) 1uf / 6.3volt. 1uf / 10 volt. 1uf / 6.3volt. c10 ( vddd ) c09 ( vcl) c08 ( c31p/n ) 1uf / 6.3 volt. 1uf / 16 volt. 1uf / 25 volt. 1uf / 10 volt. 1uf / 10 volt. 1uf / 6.3 volt. 1uf / 6.3 volt. db1 cog1 cog2 db2 cabc_pwmout db3 db4 cog1 og1 cog2 cog2 db5 db6 cabc_pwmout cabc_pwmout db7 db8 c01 1u/6.3v db10 db9 u1 cmo panel vcom 2 cog1 3 cog2 4 c22p 5 c22n 6 c21p 7 c21n 8 vgh 9 vgh 10 dummy 11 vgl 12 vgl 13 vtest 14 cabc_pwmout 15 vcl 16 vcl 17 c31p 18 c31p 19 c31n 20 c31n 21 vpp_otp 22 vpp_otp 23 vssd 24 vssd 25 vssc 26 vssc 27 vssa 28 vssa 29 vci 30 vci 31 dnc_scl 32 ncs 33 vsync 34 hsync 35 dotclk 36 de 37 nreset 38 nrd 39 nwr_scl 40 im3 41 im2 42 im1 43 im0 44 sda 45 db17 46 db16 47 db15 48 db14 49 db13 50 test8 51 db12 52 db11 53 test7 54 db10 55 db9 56 test6 57 db8 58 db7 59 test5 60 db6 61 db5 62 test4 63 db4 64 db3 65 test3 66 db2 67 db1 68 db0 69 te 70 cabc_pwmout 71 iovcc 72 iovcc 73 vddd 74 vddd 75 c12p 76 c12p 77 c12n 78 c12n 79 c11p 80 c11p 81 c11n 82 c11n 83 ddvdh 84 ddvdh 85 vreg1 86 ifsel 87 rcm0 88 rcm1 89 srgb 90 smx 91 smy 92 vcom 93 vcom 94 vcom 1 db11 db12 c02 1u/6.3v (open) db13 db14 db15 db16 db17 /wr /rd /reset c06 1u/25v vgh im1 vgl c07 1u/16v http://www..net/ datasheet pdf - http://www..net/
-p.6- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. 1.1-2 initial code for cmo 2.6 and 2.4 //################################################# #################. m51_wr_reg(u05_lcd_power_on, 0x0f); //vci & iovcc on delayx1ms(10); //reset m51_wr_reg(u05_lcd_rst, 0x01); // lcd hw rst ena ble delayx1ms(5); m51_wr_reg(u05_lcd_rst, 0x00); // lcd hw rst dis able. delayx1ms(10); //driving ability setting set_lcd_8b_reg(0xea,0x00); //ptba[15:8] set_lcd_8b_reg(0xeb,0x20); //ptba[7:0] set_lcd_8b_reg(0xec,0x0c); //stba[15:8] set_lcd_8b_reg(0xed,0xc4); //stba[7:0] set_lcd_8b_reg(0xe8,0x40); //opon[7:0] set_lcd_8b_reg(0xe9,0x38); //opon1[7:0] set_lcd_8b_reg(0xf1,0x01); //otps1b set_lcd_8b_reg(0xf2,0x10); //gen set_lcd_8b_reg(0x27,0xa3); // //gamma 2.2 setting set_lcd_8b_reg(0x40,0x01); // set_lcd_8b_reg(0x41,0x00); // set_lcd_8b_reg(0x42,0x00); // set_lcd_8b_reg(0x43,0x10); // set_lcd_8b_reg(0x44,0x0e); // set_lcd_8b_reg(0x45,0x24); // set_lcd_8b_reg(0x46,0x04); // set_lcd_8b_reg(0x47,0x50); // set_lcd_8b_reg(0x48,0x02); // set_lcd_8b_reg(0x49,0x13); // set_lcd_8b_reg(0x4a,0x19); // set_lcd_8b_reg(0x4b,0x19); // set_lcd_8b_reg(0x4c,0x16); // set_lcd_8b_reg(0x50,0x1b); // set_lcd_8b_reg(0x51,0x31); // set_lcd_8b_reg(0x52,0x2f); // set_lcd_8b_reg(0x53,0x3f); // set_lcd_8b_reg(0x54,0x3f); // set_lcd_8b_reg(0x55,0x3e); // set_lcd_8b_reg(0x56,0x2f); // set_lcd_8b_reg(0x57,0x7b); // set_lcd_8b_reg(0x58,0x09); // set_lcd_8b_reg(0x59,0x06); // set_lcd_8b_reg(0x5a,0x06); // set_lcd_8b_reg(0x5b,0x0c); // set_lcd_8b_reg(0x5c,0x1d); // set_lcd_8b_reg(0x5d,0xcc); // http://www..net/ datasheet pdf - http://www..net/
-p.7- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //power voltage setting set_lcd_8b_reg(0x1b,0x1b); //vrh=4.65v set_lcd_8b_reg(0x1a,0x01); //bt (vgh~15v,vgl~-10v,d dvdh~5v) set_lcd_8b_reg(0x24,0x2f); //vmh(vcom high voltage ~3.2v) set_lcd_8b_reg(0x25,0x57); //vml(vcom low voltage - 1.2v) //****vcom offset**/// set_lcd_8b_reg(0x23,0x88); //for flicker adjust //c an reload from otp //power on setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x01,0x00); //dp_stb='0', out deep s leep set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x80);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x90);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd0);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=0, stb=0 delayx1ms(5); //262k/65k color selection set_lcd_8b_reg(0x17,0x06); //default 0x06 262k colo r // 0x05 65k color //set panel set_lcd_8b_reg(0x36,0x00); //ss_p, gs_p,rev_p,bgr_p //display on setting set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3c); //gon=1, dte=1, d=1100 //set gram area set_lcd_8b_reg(0x02,0x00); set_lcd_8b_reg(0x03,0x00); //column start set_lcd_8b_reg(0x04,0x00); set_lcd_8b_reg(0x05,0xef); //column end set_lcd_8b_reg(0x06,0x00); set_lcd_8b_reg(0x07,0x00); //row start set_lcd_8b_reg(0x08,0x01); set_lcd_8b_reg(0x09,0x3f); //row end wr_8b_format(0x22); //start gram write http://www..net/ datasheet pdf - http://www..net/
-p.8- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // power off setting set_lcd_8b_reg(0x28,0x38); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); m51_wr_reg(u05_lcd_power_on, 0x00); //vci & iovcc off //################################################# ################# // enter idle mode setting set_lcd_8b_reg(0x18,0x34); //i/p_radj,n/p_radj, idl e mode 55hz set_lcd_8b_reg(0x2f,0x11); //idle mode line inversi on set_lcd_8b_reg(0x01,0x04); //idle='1' , enter idle mode // exit idle mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode line inver sion set_lcd_8b_reg(0x01,0x00); //idle='0', exit idle mo de //################################################# ################# // enter partial mode setting 32line set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj part ial mode 75hz set_lcd_8b_reg(0x2f,0x11); //partial mode line inve rsion set_lcd_8b_reg(0x01,0x01); //ptl='1', enter partial mode set_lcd_8b_reg(0x0a,0x00); //psl[15:8]=0x00 set_lcd_8b_reg(0x0b,0x20); //psl[7:0]=0x20 set_lcd_8b_reg(0x0c,0x00); //pel[15:8]=0x00 set_lcd_8b_reg(0x0d,0x47); //pel[7:0]=0x47 set_lcd_8b_reg(0x26,0x01); //refresh cycle=5frame // exit partial mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode, line inve rsion set_lcd_8b_reg(0x01,0x00); //ptl='0', exit partial mode http://www..net/ datasheet pdf - http://www..net/
-p.9- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // enter partial + idle mode setting 32line set_lcd_8b_reg(0x18,0x34); //i/p_radj,n/p_radj, par tial mode 55hz set_lcd_8b_reg(0x2f,0x11); // partial + idle mode l ine inversion set_lcd_8b_reg(0x01,0x09); // ptl='1' idle=1, ent er partial + idle mode set_lcd_8b_reg(0x0a,0x00); //psl[15:8]=0x00 set_lcd_8b_reg(0x0b,0x20); //psl[7:0]=0x20 set_lcd_8b_reg(0x0c,0x00); //pel[15:8]=0x00 set_lcd_8b_reg(0x0d,0x47); //pel[7:0]=0x47 set_lcd_8b_reg(0x26,0x01); //refresh cycle=5frame // exit partial + idle mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj ,nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode, line inve rsion set_lcd_8b_reg(0x01,0x00); // ptl='0' idle=0, exi t partial + idle mode //################################################# ################# // enter sleep mode setting set_lcd_8b_reg(0x28,0x38); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); // exit sleep mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x80);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x90);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd0);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3f); //gon=1, dte=1, d=1100 http://www..net/ datasheet pdf - http://www..net/
-p.10- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // enter deep sleep mode setting set_lcd_8b_reg(0x28,0x38); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); set_lcd_8b_reg(0x01,0xc0); //dp_stb[1:0]=11 // exit deep sleep mode setting set_lcd_8b_reg(0x01,0x00); //dp_stb='0', out deep s leep delayx1ms(10); set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x80);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x90);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd0);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3f); //gon=1, dte=1, d=1100 wr_8b_format(0x22); //start gram write http://www..net/ datasheet pdf - http://www..net/
-p.11- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. 1.1-3 cmo 2.0 2.2 2.4 2.8 reference fpc circuit rs /cs vci title size document number rev date: sheet of driver ic himax hx8347d a01 cmo 2.0" fpc rev a01 b 1 1 wednesday , october 08, 2008 c08 1u/10v notes 2 set ifsel="0" register-content interface mode. - vpp_otp 1 1 - c04 1u/10v notes 3 set im3~im0="1000" 80 system 18bit type i interface. notes 1 set iovcc=2.8v(1.65~3.3v);vci=2.8v(2.5~3.3v) c05 1u/10v 0 vcom sda,scl,rs vpp_otp db4 /cs te vpp_otp im3 db1 te im2 vci vci db5 iovcc db3 db2 im3 im2 im1 vcom im0 interface valid data bus 0 0 0 0 00 0 0 1 0 1 0 0 0 1 1 db15-0 db7-0 db17-10, db8-1 db17-10 1 - - id sda,scl 0 00 0 01 0 11 11 1 0 1 0 iovcc db17-0 vcl db17-0 db8-0 db17-9 8080 mcu 18 bits parallel gnd c09 1u/6.3v db15 db13 db16 j1 vci 1 vci 2 gnd 3 vcc 4 vcc 5 rest 6 db17 7 db16 8 db15 9 db14 10 db13 11 db12 12 db11 13 db10 14 db9 15 db8 16 db7 17 db6 18 db5 19 db4 20 db3 21 db2 22 db1 23 db0 24 rd 25 wr 26 rs 27 cs 28 flm 29 gnd 30 bl+ 31 bl- 32 db11 db17 db12 db14 /reset db9 db8 db6 db10 db7 /rd /wr db0 gnd te rs im0 8080 mcu 16-bits parallel type ii 8080 mcu 8-bits parallel type ii 3-wire serial interface 8080 mcu 9-bits parallel type ii 8080 mcu 16-bits parallel type i 8080 mcu 18-bits parallel type ii 8080 mcu 9-bits parallel type i 4-wire serial interface 8080 mcu 8-bits parallel type i 8080 mcu 18-bits paralle type i c01 ( c11p/n ) capacitor recommended spec. c02 ( c12p/n )(optional) 1uf / 6.3volt. c03 ( ddvdh ) c04 ( c21p/n ) c05 ( c22p/n ) c06 ( vgh ) c07 ( vgl ) c08 ( c31p/n ) c09 ( vcl) c10 ( vddd ) 1uf / 6.3volt. 1uf / 10 volt. 1uf / 10 volt. 1uf / 10 volt. 1uf / 25 volt. 1uf / 16 volt. 1uf / 6.3 volt. 1uf / 6.3 volt. 1uf / 6.3 volt. cog1 cog2 cabc_pwmout og1 cog1 cog2 cog2 cabc_pwmout cabc_pwmout vgh c06 1u/25v im1 vgl c07 1u/16v te db0 db1 db2 db4 db3 db6 db5 db8 db7 db10 db9 db12 db11 db14 db13 u1 cmo panel vcom 2 cog1 3 cog2 4 c21p 5 c21n 6 c22p 7 c22n 8 vgh 9 vgh 10 dummy 11 vgl 12 vgl 13 vtest 14 cabc_pwmout 15 vcl 16 vcl 17 c31p 18 c31p 19 c31n 20 c31n 21 vpp_otp 22 vpp_otp 23 vssd 24 vssd 25 vssc 26 vssc 27 vssc 28 vssa 29 vssa 30 vssa 31 vssa 32 vssa 33 vci 34 vci 35 dnc_scl 36 ncs 37 vsync 38 hsync 39 dotclk 40 de 41 nreset 42 nrd 43 nwr_scl 44 im3 45 im2 46 im1 47 im0 48 sda 49 db17 50 db16 51 db15 52 test9 53 db14 54 db13 55 test8 56 db12 57 db11 58 test7 59 db10 60 db9 61 test6 62 db8 63 db7 64 test5 65 db6 66 db5 67 test4 68 db4 69 db3 70 test3 71 db2 72 db1 73 db0 74 te 75 cabc_pwm_out 76 osc 77 iovcc 78 iovcc 79 vddd 80 vddd 81 vddd 82 vddd 83 vddd 84 vddd 85 c12p 86 c12p 87 c12n 88 c12n 89 c11p 90 c11p 91 c11n 92 c11n 93 ddvdh 94 vcom 1 ddvdh 95 vreg1 96 ifsel 97 vcoml_dum 98 vcomh_dum 99 rcm0 100 rcm1 101 srgb 102 smx 103 smy 104 vcom_dum 105 vcom_dum 106 ddvdh c03 1u/10v c01 1u/6.3v c02 1u/6.3v (open) vddd c10 1u/6.3v iovcc db16 db15 db17 im3 im2 im1 im0 /wr /rd /reset http://www..net/ datasheet pdf - http://www..net/
-p.12- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. 1.1-4 initial code for cmo 2.0 //################################################# #################. m51_wr_reg(u05_lcd_power_on, 0x0f); //vci & iovcc on delayx1ms(10); //reset m51_wr_reg(u05_lcd_rst, 0x01); // lcd hw rst ena ble delayx1ms(5); m51_wr_reg(u05_lcd_rst, 0x00); // lcd hw rst dis able. delayx1ms(10); //driving ability setting set_lcd_8b_reg(0xea,0x00); //ptba[15:8] set_lcd_8b_reg(0xeb,0x20); //ptba[7:0] set_lcd_8b_reg(0xec,0x0c); //stba[15:8] set_lcd_8b_reg(0xed,0xc4); //stba[7:0] set_lcd_8b_reg(0xe8,0x40); //opon[7:0] set_lcd_8b_reg(0xe9,0x38); //opon1[7:0] set_lcd_8b_reg(0xf1,0x01); //otps1b set_lcd_8b_reg(0xf2,0x10); //gen set_lcd_8b_reg(0x27,0xa3); // //gamma 2.2 setting set_lcd_8b_reg(0x40,0x00); // set_lcd_8b_reg(0x41,0x00); // set_lcd_8b_reg(0x42,0x01); // set_lcd_8b_reg(0x43,0x12); // set_lcd_8b_reg(0x44,0x10); // set_lcd_8b_reg(0x45,0x26); // set_lcd_8b_reg(0x46,0x08); // set_lcd_8b_reg(0x47,0x54); // set_lcd_8b_reg(0x48,0x02); // set_lcd_8b_reg(0x49,0x15); // set_lcd_8b_reg(0x4a,0x19); // set_lcd_8b_reg(0x4b,0x19); // set_lcd_8b_reg(0x4c,0x16); // set_lcd_8b_reg(0x50,0x19); // set_lcd_8b_reg(0x51,0x2f); // set_lcd_8b_reg(0x52,0x2d); // set_lcd_8b_reg(0x53,0x3e); // set_lcd_8b_reg(0x54,0x3f); // set_lcd_8b_reg(0x55,0x3f); // set_lcd_8b_reg(0x56,0x2b); // set_lcd_8b_reg(0x57,0x77); // set_lcd_8b_reg(0x58,0x09); // set_lcd_8b_reg(0x59,0x06); // set_lcd_8b_reg(0x5a,0x06); // set_lcd_8b_reg(0x5b,0x0a); // set_lcd_8b_reg(0x5c,0x1d); // set_lcd_8b_reg(0x5d,0xcc); // //power voltage setting http://www..net/ datasheet pdf - http://www..net/
-p.13- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. set_lcd_8b_reg(0x1b,0x1b); //vrh=4.65v set_lcd_8b_reg(0x1a,0x01); //bt (vgh~15v,vgl~-10v,d dvdh~5v) set_lcd_8b_reg(0x24,0x2f); //vmh(vcom high voltage ~3.2v) set_lcd_8b_reg(0x25,0x57); //vml(vcom low voltage - 1.2v) //****vcom offset**/// set_lcd_8b_reg(0x23,0x79); //for flicker adjust //c an reload from otp //power on setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x01,0x00); //dp_stb='0', out deep s leep set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x80);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x90);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd0);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=0, stb=0 delayx1ms(5); //262k/65k color selection set_lcd_8b_reg(0x17,0x06); //default 0x06 262k colo r // 0x05 65k color //set panel set_lcd_8b_reg(0x36,0x00); //ss_p, gs_p,rev_p,bgr_p //display on setting set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3c); //gon=1, dte=1, d=1100 //set gram area set_lcd_8b_reg(0x02,0x00); set_lcd_8b_reg(0x03,0x00); //column start set_lcd_8b_reg(0x04,0x00); set_lcd_8b_reg(0x05,0xef); //column end set_lcd_8b_reg(0x06,0x00); set_lcd_8b_reg(0x07,0x00); //row start set_lcd_8b_reg(0x08,0x01); set_lcd_8b_reg(0x09,0x3f); //row end wr_8b_format(0x22); //start gram write http://www..net/ datasheet pdf - http://www..net/
-p.14- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // power off setting set_lcd_8b_reg(0x28,0x38); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); m51_wr_reg(u05_lcd_power_on, 0x00); //vci & iovcc off //################################################# ################# // enter idle mode setting set_lcd_8b_reg(0x18,0x34); //i/p_radj,n/p_radj, idl e mode 55hz set_lcd_8b_reg(0x2f,0x11); //idle mode line inversi on set_lcd_8b_reg(0x01,0x04); //idle='1' , enter idle mode // exit idle mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode line inver sion set_lcd_8b_reg(0x01,0x00); //idle='0', exit idle mo de //################################################# ################# // enter partial mode setting 32line set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj part ial mode 75hz set_lcd_8b_reg(0x2f,0x11); //partial mode line inve rsion set_lcd_8b_reg(0x01,0x01); //ptl='1', enter partial mode set_lcd_8b_reg(0x0a,0x00); //psl[15:8]=0x00 set_lcd_8b_reg(0x0b,0x20); //psl[7:0]=0x20 set_lcd_8b_reg(0x0c,0x00); //pel[15:8]=0x00 set_lcd_8b_reg(0x0d,0x47); //pel[7:0]=0x47 set_lcd_8b_reg(0x26,0x01); //refresh cycle=5frame // exit partial mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode, line inve rsion set_lcd_8b_reg(0x01,0x00); //ptl='0', exit partial mode http://www..net/ datasheet pdf - http://www..net/
-p.15- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // enter partial + idle mode setting 32line set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, par tial mode 55hz set_lcd_8b_reg(0x2f,0x11); // partial + idle mode l ine inversion set_lcd_8b_reg(0x01,0x09); // ptl='1' idle=1, ent er partial + idle mode set_lcd_8b_reg(0x0a,0x00); //psl[15:8]=0x00 set_lcd_8b_reg(0x0b,0x20); //psl[7:0]=0x20 set_lcd_8b_reg(0x0c,0x00); //pel[15:8]=0x00 set_lcd_8b_reg(0x0d,0x47); //pel[7:0]=0x47 set_lcd_8b_reg(0x26,0x01); //refresh cycle=5frame // exit partial + idle mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj ,nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode, line inve rsion set_lcd_8b_reg(0x01,0x00); // ptl='0' idle=0, exi t partial + idle mode //################################################# ################# // enter sleep mode setting set_lcd_8b_reg(0x28,0xb8); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); // exit sleep mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x80);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x90);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd0);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3f); //gon=1, dte=1, d=1100 http://www..net/ datasheet pdf - http://www..net/
-p.16- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // enter deep sleep mode setting set_lcd_8b_reg(0x28,0xb8); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); set_lcd_8b_reg(0x01,0xc0); //dp_stb[1:0]=11 // exit deep sleep mode setting set_lcd_8b_reg(0x01,0x00); //dp_stb='0', out deep s leep delayx1ms(10); set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x80);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x90);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd0);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3f); //gon=1, dte=1, d=1100 wr_8b_format(0x22); //start gram write http://www..net/ datasheet pdf - http://www..net/
-p.17- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. 1.1-5 initial code for cmo 2.2 //################################################# #################. m51_wr_reg(u05_lcd_power_on, 0x0f); //vci & iovcc on delayx1ms(10); //reset m51_wr_reg(u05_lcd_rst, 0x01); // lcd hw rst ena ble delayx1ms(5); m51_wr_reg(u05_lcd_rst, 0x00); // lcd hw rst dis able. delayx1ms(10); //driving ability setting set_lcd_8b_reg(0xea,0x00); //ptba[15:8] set_lcd_8b_reg(0xeb,0x20); //ptba[7:0] set_lcd_8b_reg(0xec,0x0c); //stba[15:8] set_lcd_8b_reg(0xed,0xc4); //stba[7:0] set_lcd_8b_reg(0xe8,0x40); //opon[7:0] set_lcd_8b_reg(0xe9,0x38); //opon1[7:0] set_lcd_8b_reg(0xf1,0x01); //otps1b set_lcd_8b_reg(0xf2,0x10); //gen set_lcd_8b_reg(0x27,0xa3); // //gamma 2.2 setting set_lcd_8b_reg(0x40,0x00); // set_lcd_8b_reg(0x41,0x00); // set_lcd_8b_reg(0x42,0x01); // set_lcd_8b_reg(0x43,0x12); // set_lcd_8b_reg(0x44,0x10); // set_lcd_8b_reg(0x45,0x26); // set_lcd_8b_reg(0x46,0x08); // set_lcd_8b_reg(0x47,0x53); // set_lcd_8b_reg(0x48,0x02); // set_lcd_8b_reg(0x49,0x15); // set_lcd_8b_reg(0x4a,0x19); // set_lcd_8b_reg(0x4b,0x19); // set_lcd_8b_reg(0x4c,0x16); // set_lcd_8b_reg(0x50,0x19); // set_lcd_8b_reg(0x51,0x2f); // set_lcd_8b_reg(0x52,0x2d); // set_lcd_8b_reg(0x53,0x3e); // set_lcd_8b_reg(0x54,0x3f); // set_lcd_8b_reg(0x55,0x3f); // set_lcd_8b_reg(0x56,0x2c); // set_lcd_8b_reg(0x57,0x77); // set_lcd_8b_reg(0x58,0x09); // set_lcd_8b_reg(0x59,0x06); // set_lcd_8b_reg(0x5a,0x06); // set_lcd_8b_reg(0x5b,0x0a); // set_lcd_8b_reg(0x5c,0x1d); // set_lcd_8b_reg(0x5d,0xcc); // //power voltage setting http://www..net/ datasheet pdf - http://www..net/
-p.18- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. set_lcd_8b_reg(0x1b,0x1b); //vrh=4.65v set_lcd_8b_reg(0x1a,0x01); //bt (vgh~15v,vgl~-10v,d dvdh~5v) set_lcd_8b_reg(0x24,0x2f); //vmh(vcom high voltage ~3.2v) set_lcd_8b_reg(0x25,0x57); //vml(vcom low voltage - 1.2v) //****vcom offset**/// set_lcd_8b_reg(0x23,0x97); //for flicker adjust //c an reload from otp //power on setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x01,0x00); //dp_stb='0', out deep s leep set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x80);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x90);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd0);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=0, stb=0 delayx1ms(5); //262k/65k color selection set_lcd_8b_reg(0x17,0x06); //default 0x06 262k colo r // 0x05 65k color //set panel set_lcd_8b_reg(0x36,0x00); //ss_p, gs_p,rev_p,bgr_p //display on setting set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3c); //gon=1, dte=1, d=1100 //set gram area set_lcd_8b_reg(0x02,0x00); set_lcd_8b_reg(0x03,0x00); //column start set_lcd_8b_reg(0x04,0x00); set_lcd_8b_reg(0x05,0xef); //column end set_lcd_8b_reg(0x06,0x00); set_lcd_8b_reg(0x07,0x00); //row start set_lcd_8b_reg(0x08,0x01); set_lcd_8b_reg(0x09,0x3f); //row end wr_8b_format(0x22); //start gram write http://www..net/ datasheet pdf - http://www..net/
-p.19- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // power off setting set_lcd_8b_reg(0x28,0x38); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); m51_wr_reg(u05_lcd_power_on, 0x00); //vci & iovcc off //################################################# ################# // enter idle mode setting set_lcd_8b_reg(0x18,0x34); //i/p_radj,n/p_radj, idl e mode 55hz set_lcd_8b_reg(0x2f,0x11); //idle mode line inversi on set_lcd_8b_reg(0x01,0x04); //idle='1' , enter idle mode // exit idle mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode line inver sion set_lcd_8b_reg(0x01,0x00); //idle='0', exit idle mo de //################################################# ################# // enter partial mode setting 32line set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj part ial mode 75hz set_lcd_8b_reg(0x2f,0x11); //partial mode line inve rsion set_lcd_8b_reg(0x01,0x01); //ptl='1', enter partial mode set_lcd_8b_reg(0x0a,0x00); //psl[15:8]=0x00 set_lcd_8b_reg(0x0b,0x20); //psl[7:0]=0x20 set_lcd_8b_reg(0x0c,0x00); //pel[15:8]=0x00 set_lcd_8b_reg(0x0d,0x47); //pel[7:0]=0x47 set_lcd_8b_reg(0x26,0x01); //refresh cycle=5frame // exit partial mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode, line inve rsion set_lcd_8b_reg(0x01,0x00); //ptl='0', exit partial mode http://www..net/ datasheet pdf - http://www..net/
-p.20- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // enter partial + idle mode setting 32line set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, par tial mode 55hz set_lcd_8b_reg(0x2f,0x11); // partial + idle mode l ine inversion set_lcd_8b_reg(0x01,0x09); // ptl='1' idle=1, ent er partial + idle mode set_lcd_8b_reg(0x0a,0x00); //psl[15:8]=0x00 set_lcd_8b_reg(0x0b,0x20); //psl[7:0]=0x20 set_lcd_8b_reg(0x0c,0x00); //pel[15:8]=0x00 set_lcd_8b_reg(0x0d,0x47); //pel[7:0]=0x47 set_lcd_8b_reg(0x26,0x01); //refresh cycle=5frame // exit partial + idle mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj ,nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode, line inve rsion set_lcd_8b_reg(0x01,0x00); // ptl='0' idle=0, exi t partial + idle mode //################################################# ################# // enter sleep mode setting set_lcd_8b_reg(0x28,0xb8); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); // exit sleep mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x80);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x90);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd0);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3f); //gon=1, dte=1, d=1100 http://www..net/ datasheet pdf - http://www..net/
-p.21- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // enter deep sleep mode setting set_lcd_8b_reg(0x28,0xb8); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); set_lcd_8b_reg(0x01,0xc0); //dp_stb[1:0]=11 // exit deep sleep mode setting set_lcd_8b_reg(0x01,0x00); //dp_stb='0', out deep s leep delayx1ms(10); set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x80);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x90);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd0);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3f); //gon=1, dte=1, d=1100 wr_8b_format(0x22); //start gram write http://www..net/ datasheet pdf - http://www..net/
-p.22- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. 1.1-6 initial code for cmo 2.8 //################################################# #################. m51_wr_reg(u05_lcd_power_on, 0x0f); //vci & iovcc on delayx1ms(10); //reset m51_wr_reg(u05_lcd_rst, 0x01); // lcd hw rst ena ble delayx1ms(5); m51_wr_reg(u05_lcd_rst, 0x00); // lcd hw rst dis able. delayx1ms(10); //driving ability setting set_lcd_8b_reg(0xea,0x00); //ptba[15:8] set_lcd_8b_reg(0xeb,0x20); //ptba[7:0] set_lcd_8b_reg(0xec,0x0c); //stba[15:8] set_lcd_8b_reg(0xed,0xc4); //stba[7:0] set_lcd_8b_reg(0xe8,0x40); //opon[7:0] set_lcd_8b_reg(0xe9,0x38); //opon1[7:0] set_lcd_8b_reg(0xf1,0x01); //otps1b set_lcd_8b_reg(0xf2,0x10); //gen set_lcd_8b_reg(0x27,0xa3); // //gamma 2.2 setting set_lcd_8b_reg(0x40,0x00); // set_lcd_8b_reg(0x41,0x00); // set_lcd_8b_reg(0x42,0x01); // set_lcd_8b_reg(0x43,0x13); // set_lcd_8b_reg(0x44,0x10); // set_lcd_8b_reg(0x45,0x26); // set_lcd_8b_reg(0x46,0x08); // set_lcd_8b_reg(0x47,0x51); // set_lcd_8b_reg(0x48,0x02); // set_lcd_8b_reg(0x49,0x12); // set_lcd_8b_reg(0x4a,0x18); // set_lcd_8b_reg(0x4b,0x19); // set_lcd_8b_reg(0x4c,0x14); // set_lcd_8b_reg(0x50,0x19); // set_lcd_8b_reg(0x51,0x2f); // set_lcd_8b_reg(0x52,0x2c); // set_lcd_8b_reg(0x53,0x3e); // set_lcd_8b_reg(0x54,0x3f); // set_lcd_8b_reg(0x55,0x3f); // set_lcd_8b_reg(0x56,0x2e); // set_lcd_8b_reg(0x57,0x77); // set_lcd_8b_reg(0x58,0x0b); // set_lcd_8b_reg(0x59,0x06); // set_lcd_8b_reg(0x5a,0x07); // set_lcd_8b_reg(0x5b,0x0d); // set_lcd_8b_reg(0x5c,0x1d); // set_lcd_8b_reg(0x5d,0xcc); // //power voltage setting http://www..net/ datasheet pdf - http://www..net/
-p.23- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. set_lcd_8b_reg(0x1b,0x1b); //vrh=4.65v set_lcd_8b_reg(0x1a,0x01); //bt (vgh~15v,vgl~-10v,d dvdh~5v) set_lcd_8b_reg(0x24,0x2f); //vmh(vcom high voltage ~3.2v) set_lcd_8b_reg(0x25,0x57); //vml(vcom low voltage - 1.2v) //****vcom offset**/// set_lcd_8b_reg(0x23,0x86); //for flicker adjust //c an reload from otp //power on setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x01,0x00); //dp_stb='0', out deep s leep set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x80);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x90);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd0);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=0, stb=0 delayx1ms(5); //262k/65k color selection set_lcd_8b_reg(0x17,0x06); //default 0x06 262k colo r // 0x05 65k color //set panel set_lcd_8b_reg(0x36,0x00); //ss_p, gs_p,rev_p,bgr_p //display on setting set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3c); //gon=1, dte=1, d=1100 //set gram area set_lcd_8b_reg(0x02,0x00); set_lcd_8b_reg(0x03,0x00); //column start set_lcd_8b_reg(0x04,0x00); set_lcd_8b_reg(0x05,0xef); //column end set_lcd_8b_reg(0x06,0x00); set_lcd_8b_reg(0x07,0x00); //row start set_lcd_8b_reg(0x08,0x01); set_lcd_8b_reg(0x09,0x3f); //row end wr_8b_format(0x22); //start gram write http://www..net/ datasheet pdf - http://www..net/
-p.24- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // power off setting set_lcd_8b_reg(0x28,0x38); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); m51_wr_reg(u05_lcd_power_on, 0x00); //vci & iovcc off //################################################# ################# // enter idle mode setting set_lcd_8b_reg(0x18,0x34); //i/p_radj,n/p_radj, idl e mode 55hz set_lcd_8b_reg(0x2f,0x11); //idle mode line inversi on set_lcd_8b_reg(0x01,0x04); //idle='1' , enter idle mode // exit idle mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode line inver sion set_lcd_8b_reg(0x01,0x00); //idle='0', exit idle mo de //################################################# ################# // enter partial mode setting 32line set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj part ial mode 75hz set_lcd_8b_reg(0x2f,0x11); //partial mode line inve rsion set_lcd_8b_reg(0x01,0x01); //ptl='1', enter partial mode set_lcd_8b_reg(0x0a,0x00); //psl[15:8]=0x00 set_lcd_8b_reg(0x0b,0x20); //psl[7:0]=0x20 set_lcd_8b_reg(0x0c,0x00); //pel[15:8]=0x00 set_lcd_8b_reg(0x0d,0x47); //pel[7:0]=0x47 set_lcd_8b_reg(0x26,0x01); //refresh cycle=5frame // exit partial mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode, line inve rsion set_lcd_8b_reg(0x01,0x00); //ptl='0', exit partial mode http://www..net/ datasheet pdf - http://www..net/
-p.25- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // enter partial + idle mode setting 32line set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, par tial mode 55hz set_lcd_8b_reg(0x2f,0x11); // partial + idle mode l ine inversion set_lcd_8b_reg(0x01,0x09); // ptl='1' idle=1, ent er partial + idle mode set_lcd_8b_reg(0x0a,0x00); //psl[15:8]=0x00 set_lcd_8b_reg(0x0b,0x20); //psl[7:0]=0x20 set_lcd_8b_reg(0x0c,0x00); //pel[15:8]=0x00 set_lcd_8b_reg(0x0d,0x47); //pel[7:0]=0x47 set_lcd_8b_reg(0x26,0x01); //refresh cycle=5frame // exit partial + idle mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj ,nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode, line inve rsion set_lcd_8b_reg(0x01,0x00); // ptl='0' idle=0, exi t partial + idle mode //################################################# ################# // enter sleep mode setting set_lcd_8b_reg(0x28,0xb8); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); // exit sleep mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x80);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x90);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd0);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3f); //gon=1, dte=1, d=1100 http://www..net/ datasheet pdf - http://www..net/
-p.26- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // enter deep sleep mode setting set_lcd_8b_reg(0x28,0xb8); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); set_lcd_8b_reg(0x01,0xc0); //dp_stb[1:0]=11 // exit deep sleep mode setting set_lcd_8b_reg(0x01,0x00); //dp_stb='0', out deep s leep delayx1ms(10); set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x80);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x90);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd0);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3f); //gon=1, dte=1, d=1100 wr_8b_format(0x22); //start gram write http://www..net/ datasheet pdf - http://www..net/
-p.27- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. 1.1-7 initial code for cmo 2.4 //################################################# #################. m51_wr_reg(u05_lcd_power_on, 0x0f); //vci & iovcc on delayx1ms(10); //reset m51_wr_reg(u05_lcd_rst, 0x01); // lcd hw rst ena ble delayx1ms(5); m51_wr_reg(u05_lcd_rst, 0x00); // lcd hw rst dis able. delayx1ms(10); //driving ability setting set_lcd_8b_reg(0xea,0x00); //ptba[15:8] set_lcd_8b_reg(0xeb,0x20); //ptba[7:0] set_lcd_8b_reg(0xec,0x0c); //stba[15:8] set_lcd_8b_reg(0xed,0xc4); //stba[7:0] set_lcd_8b_reg(0xe8,0x40); //opon[7:0] set_lcd_8b_reg(0xe9,0x38); //opon1[7:0] set_lcd_8b_reg(0xf1,0x01); //otps1b set_lcd_8b_reg(0xf2,0x10); //gen set_lcd_8b_reg(0x27,0xa3); // //gamma 2.2 setting set_lcd_8b_reg(0x40,0x01); // set_lcd_8b_reg(0x41,0x00); // set_lcd_8b_reg(0x42,0x00); // set_lcd_8b_reg(0x43,0x10); // set_lcd_8b_reg(0x44,0x0e); // set_lcd_8b_reg(0x45,0x24); // set_lcd_8b_reg(0x46,0x04); // set_lcd_8b_reg(0x47,0x50); // set_lcd_8b_reg(0x48,0x02); // set_lcd_8b_reg(0x49,0x13); // set_lcd_8b_reg(0x4a,0x19); // set_lcd_8b_reg(0x4b,0x19); // set_lcd_8b_reg(0x4c,0x16); // set_lcd_8b_reg(0x50,0x1b); // set_lcd_8b_reg(0x51,0x31); // set_lcd_8b_reg(0x52,0x2f); // set_lcd_8b_reg(0x53,0x3f); // set_lcd_8b_reg(0x54,0x3f); // set_lcd_8b_reg(0x55,0x3e); // set_lcd_8b_reg(0x56,0x2f); // set_lcd_8b_reg(0x57,0x7b); // set_lcd_8b_reg(0x58,0x09); // set_lcd_8b_reg(0x59,0x06); // set_lcd_8b_reg(0x5a,0x06); // set_lcd_8b_reg(0x5b,0x0c); // set_lcd_8b_reg(0x5c,0x1d); // set_lcd_8b_reg(0x5d,0xcc); // //power voltage setting http://www..net/ datasheet pdf - http://www..net/
-p.28- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. set_lcd_8b_reg(0x1b,0x1b); //vrh=4.65v set_lcd_8b_reg(0x1a,0x01); //bt (vgh~15v,vgl~-10v,d dvdh~5v) set_lcd_8b_reg(0x24,0x2f); //vmh(vcom high voltage ~3.2v) set_lcd_8b_reg(0x25,0x57); //vml(vcom low voltage - 1.2v) //****vcom offset**/// set_lcd_8b_reg(0x23,0x86); //for flicker adjust //c an reload from otp //power on setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x01,0x00); //dp_stb='0', out deep s leep set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x80);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x90);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd0);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=0, stb=0 delayx1ms(5); //262k/65k color selection set_lcd_8b_reg(0x17,0x06); //default 0x06 262k colo r // 0x05 65k color //set panel set_lcd_8b_reg(0x36,0x00); //ss_p, gs_p,rev_p,bgr_p //display on setting set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3c); //gon=1, dte=1, d=1100 //set gram area set_lcd_8b_reg(0x02,0x00); set_lcd_8b_reg(0x03,0x00); //column start set_lcd_8b_reg(0x04,0x00); set_lcd_8b_reg(0x05,0xef); //column end set_lcd_8b_reg(0x06,0x00); set_lcd_8b_reg(0x07,0x00); //row start set_lcd_8b_reg(0x08,0x01); set_lcd_8b_reg(0x09,0x3f); //row end wr_8b_format(0x22); //start gram write http://www..net/ datasheet pdf - http://www..net/
-p.29- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // power off setting set_lcd_8b_reg(0x28,0x38); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); m51_wr_reg(u05_lcd_power_on, 0x00); //vci & iovcc off //################################################# ################# // enter idle mode setting set_lcd_8b_reg(0x18,0x34); //i/p_radj,n/p_radj, idl e mode 55hz set_lcd_8b_reg(0x2f,0x11); //idle mode line inversi on set_lcd_8b_reg(0x01,0x04); //idle='1' , enter idle mode // exit idle mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode line inver sion set_lcd_8b_reg(0x01,0x00); //idle='0', exit idle mo de //################################################# ################# // enter partial mode setting 32line set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj part ial mode 75hz set_lcd_8b_reg(0x2f,0x11); //partial mode line inve rsion set_lcd_8b_reg(0x01,0x01); //ptl='1', enter partial mode set_lcd_8b_reg(0x0a,0x00); //psl[15:8]=0x00 set_lcd_8b_reg(0x0b,0x20); //psl[7:0]=0x20 set_lcd_8b_reg(0x0c,0x00); //pel[15:8]=0x00 set_lcd_8b_reg(0x0d,0x47); //pel[7:0]=0x47 set_lcd_8b_reg(0x26,0x01); //refresh cycle=5frame // exit partial mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode, line inve rsion set_lcd_8b_reg(0x01,0x00); //ptl='0', exit partial mode http://www..net/ datasheet pdf - http://www..net/
-p.30- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // enter partial + idle mode setting 32line set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, par tial mode 55hz set_lcd_8b_reg(0x2f,0x11); // partial + idle mode l ine inversion set_lcd_8b_reg(0x01,0x09); // ptl='1' idle=1, ent er partial + idle mode set_lcd_8b_reg(0x0a,0x00); //psl[15:8]=0x00 set_lcd_8b_reg(0x0b,0x20); //psl[7:0]=0x20 set_lcd_8b_reg(0x0c,0x00); //pel[15:8]=0x00 set_lcd_8b_reg(0x0d,0x47); //pel[7:0]=0x47 set_lcd_8b_reg(0x26,0x01); //refresh cycle=5frame // exit partial + idle mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj ,nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode, line inve rsion set_lcd_8b_reg(0x01,0x00); // ptl='0' idle=0, exi t partial + idle mode //################################################# ################# // enter sleep mode setting set_lcd_8b_reg(0x28,0xb8); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); // exit sleep mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x80);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x90);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd0);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3f); //gon=1, dte=1, d=1100 http://www..net/ datasheet pdf - http://www..net/
-p.31- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // enter deep sleep mode setting set_lcd_8b_reg(0x28,0xb8); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); set_lcd_8b_reg(0x01,0xc0); //dp_stb[1:0]=11 // exit deep sleep mode setting set_lcd_8b_reg(0x01,0x00); //dp_stb='0', out deep s leep delayx1ms(10); set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x80);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x90);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd0);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3f); //gon=1, dte=1, d=1100 wr_8b_format(0x22); //start gram write http://www..net/ datasheet pdf - http://www..net/
-p.32- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. 1.1-8 initial code for cmo 2223 panel //################################################# #################. m51_wr_reg(u05_lcd_power_on, 0x0f); //vci & iovcc on delayx1ms(10); //reset m51_wr_reg(u05_lcd_rst, 0x01); // lcd hw rst ena ble delayx1ms(5); m51_wr_reg(u05_lcd_rst, 0x00); // lcd hw rst dis able. delayx1ms(10); //driving ability setting set_lcd_8b_reg(0xea,0x00); //ptba[15:8] set_lcd_8b_reg(0xeb,0x20); //ptba[7:0] set_lcd_8b_reg(0xec,0x0c); //stba[15:8] set_lcd_8b_reg(0xed,0xc4); //stba[7:0] set_lcd_8b_reg(0xe8,0x44); //opon[7:0] set_lcd_8b_reg(0xe9,0x38); //opon1[7:0] set_lcd_8b_reg(0xf1,0x01); //otps1b set_lcd_8b_reg(0xf2,0x10); //gen set_lcd_8b_reg(0x27,0xa3); // //gamma 2.2 setting set_lcd_8b_reg(0x40,0x07); set_lcd_8b_reg(0x41,0x0c); set_lcd_8b_reg(0x42,0x09); set_lcd_8b_reg(0x43,0x07); set_lcd_8b_reg(0x44,0x06); set_lcd_8b_reg(0x45,0x21); set_lcd_8b_reg(0x46,0x00); set_lcd_8b_reg(0x47,0x3a); set_lcd_8b_reg(0x48,0x06); set_lcd_8b_reg(0x49,0x11); set_lcd_8b_reg(0x4a,0x18); set_lcd_8b_reg(0x4b,0x18); set_lcd_8b_reg(0x4c,0x1f); set_lcd_8b_reg(0x50,0x08); set_lcd_8b_reg(0x51,0x2e); set_lcd_8b_reg(0x52,0x2d); set_lcd_8b_reg(0x53,0x20); set_lcd_8b_reg(0x54,0x1e); set_lcd_8b_reg(0x55,0x21); set_lcd_8b_reg(0x56,0x2f); set_lcd_8b_reg(0x57,0x71); set_lcd_8b_reg(0x58,0x01); set_lcd_8b_reg(0x59,0x06); set_lcd_8b_reg(0x5a,0x08); set_lcd_8b_reg(0x5b,0x0e); set_lcd_8b_reg(0x5c,0x18); set_lcd_8b_reg(0x5d,0xff); //power voltage setting set_lcd_8b_reg(0x1b,0x2e); //vreg1 set_lcd_8b_reg(0x1a,0x01); set_lcd_8b_reg(0x24,0x64); http://www..net/ datasheet pdf - http://www..net/
-p.33- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. set_lcd_8b_reg(0x25,0x21); //****vcom offset**/// set_lcd_8b_reg(0x23,0x71); set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x01,0x00); //dp_stb='0', out deep s leep set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x82);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=1, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x92);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=1, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd2);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=1, stb=0 delayx1ms(5); //262k/65k color selection set_lcd_8b_reg(0x17,0x06); //default 0x06 262k colo r // 0x05 65k color //set panel set_lcd_8b_reg(0x36,0x03); //ss_p, gs_p,rev_p,bgr_p //display on setting//display on setting set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3c); //gon=1, dte=1, d=1100 //set gram area set_lcd_8b_reg(0x02,0x00); set_lcd_8b_reg(0x03,0x00); //column start set_lcd_8b_reg(0x04,0x00); set_lcd_8b_reg(0x05,0xef); //column end set_lcd_8b_reg(0x06,0x00); set_lcd_8b_reg(0x07,0x00); //row start set_lcd_8b_reg(0x08,0x01); set_lcd_8b_reg(0x09,0x3f); //row end wr_8b_format(0x22); //start gram write http://www..net/ datasheet pdf - http://www..net/
-p.34- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // power off setting set_lcd_8b_reg(0x28,0x38); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); m51_wr_reg(u05_lcd_power_on, 0x00); //vci & iovcc off //################################################# ################# // enter idle mode setting set_lcd_8b_reg(0x18,0x34); //i/p_radj,n/p_radj, idl e mode 55hz set_lcd_8b_reg(0x2f,0x11); //idle mode line inversi on set_lcd_8b_reg(0x01,0x04); //idle='1' , enter idle mode // exit idle mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode line inver sion set_lcd_8b_reg(0x01,0x00); //idle='0', exit idle mo de //################################################# ################# // enter partial mode setting 32line set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj part ial mode 75hz set_lcd_8b_reg(0x2f,0x11); //partial mode line inve rsion set_lcd_8b_reg(0x01,0x01); //ptl='1', enter partial mode set_lcd_8b_reg(0x0a,0x00); //psl[15:8]=0x00 set_lcd_8b_reg(0x0b,0x20); //psl[7:0]=0x20 set_lcd_8b_reg(0x0c,0x00); //pel[15:8]=0x00 set_lcd_8b_reg(0x0d,0x47); //pel[7:0]=0x47 set_lcd_8b_reg(0x26,0x01); //refresh cycle=5frame // exit partial mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode, line inve rsion set_lcd_8b_reg(0x01,0x00); //ptl='0', exit partial mode http://www..net/ datasheet pdf - http://www..net/
-p.35- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // enter partial + idle mode setting 32line set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, par tial mode 55hz set_lcd_8b_reg(0x2f,0x11); // partial + idle mode l ine inversion set_lcd_8b_reg(0x01,0x09); // ptl='1' idle=1, ent er partial + idle mode set_lcd_8b_reg(0x0a,0x00); //psl[15:8]=0x00 set_lcd_8b_reg(0x0b,0x20); //psl[7:0]=0x20 set_lcd_8b_reg(0x0c,0x00); //pel[15:8]=0x00 set_lcd_8b_reg(0x0d,0x47); //pel[7:0]=0x47 set_lcd_8b_reg(0x26,0x01); //refresh cycle=5frame // exit partial + idle mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj ,nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode, line inve rsion set_lcd_8b_reg(0x01,0x00); // ptl='0' idle=0, exi t partial + idle mode //################################################# ################# // enter sleep mode setting set_lcd_8b_reg(0x28,0xb8); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); // exit sleep mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x82);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=1, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x92);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=1, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd2);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=1, stb=0 delayx1ms(5); set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3c); //gon=1, dte=1, d=1100 http://www..net/ datasheet pdf - http://www..net/
-p.36- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // enter deep sleep mode setting set_lcd_8b_reg(0x28,0xb8); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); set_lcd_8b_reg(0x01,0xc0); //dp_stb[1:0]=11 // exit deep sleep mode setting set_lcd_8b_reg(0x01,0x00); //dp_stb='0', out deep s leep delayx1ms(10); set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x82);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=1, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x92);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=1, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd2);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=1, stb=0 delayx1ms(5); set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3c); //gon=1, dte=1, d=1100 wr_8b_format(0x22); //start gram write http://www..net/ datasheet pdf - http://www..net/
-p.37- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. 1.1-9 initial code for cmo 2807 panel //################################################# #################. m51_wr_reg(u05_lcd_power_on, 0x0f); //vci & iovcc on delayx1ms(10); //reset m51_wr_reg(u05_lcd_rst, 0x01); // lcd hw rst ena ble delayx1ms(5); m51_wr_reg(u05_lcd_rst, 0x00); // lcd hw rst dis able. delayx1ms(10); //driving ability setting set_lcd_8b_reg(0xea,0x00); //ptba[15:8] set_lcd_8b_reg(0xeb,0x20); //ptba[7:0] set_lcd_8b_reg(0xec,0x0c); //stba[15:8] set_lcd_8b_reg(0xed,0xc4); //stba[7:0] set_lcd_8b_reg(0xe8,0x40); //opon[7:0] set_lcd_8b_reg(0xe9,0x38); //opon1[7:0] set_lcd_8b_reg(0xf1,0x01); //otps1b set_lcd_8b_reg(0xf2,0x10); //gen set_lcd_8b_reg(0x27,0xa3); // //gamma 2.2 setting set_lcd_8b_reg(0x40,0x01); set_lcd_8b_reg(0x41,0x07); set_lcd_8b_reg(0x42,0x06); set_lcd_8b_reg(0x43,0x0a); set_lcd_8b_reg(0x44,0x0c); set_lcd_8b_reg(0x45,0x3d); set_lcd_8b_reg(0x46,0x02); set_lcd_8b_reg(0x47,0x43); set_lcd_8b_reg(0x48,0x07); set_lcd_8b_reg(0x49,0x14); set_lcd_8b_reg(0x4a,0x19); set_lcd_8b_reg(0x4b,0x1a); set_lcd_8b_reg(0x4c,0x1e); set_lcd_8b_reg(0x50,0x02); set_lcd_8b_reg(0x51,0x33); set_lcd_8b_reg(0x52,0x35); set_lcd_8b_reg(0x53,0x39); set_lcd_8b_reg(0x54,0x38); set_lcd_8b_reg(0x55,0x3e); set_lcd_8b_reg(0x56,0x3c); set_lcd_8b_reg(0x57,0x7d); set_lcd_8b_reg(0x58,0x01); set_lcd_8b_reg(0x59,0x05); set_lcd_8b_reg(0x5a,0x06); set_lcd_8b_reg(0x5b,0x0b); set_lcd_8b_reg(0x5c,0x18); set_lcd_8b_reg(0x5d,0xff); //power voltage setting set_lcd_8b_reg(0x1b,0x1b); //vrh=4.65v set_lcd_8b_reg(0x1a,0x01); //bt (vgh~15v,vgl~-10v,d dvdh~5v) set_lcd_8b_reg(0x24,0x45); //vmh(vcom high voltage ~3.53v) http://www..net/ datasheet pdf - http://www..net/
-p.38- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. set_lcd_8b_reg(0x25,0x1f); //vml(vcom low voltage - 2.03v) //****vcom offset**/// set_lcd_8b_reg(0x23,0x8a); //for flicker adjust //c an reload from otp //power on setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x01,0x00); //dp_stb='0', out deep s leep set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x80);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x90);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd0);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=0, stb=0 delayx1ms(5); //262k/65k color selection set_lcd_8b_reg(0x17,0x06); //default 0x06 262k colo r // 0x05 65k color //set panel set_lcd_8b_reg(0x36,0x02); //ss_p, gs_p,rev_p,bgr_p //display on setting set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3c); //gon=1, dte=1, d=1100 //set gram area set_lcd_8b_reg(0x02,0x00); set_lcd_8b_reg(0x03,0x00); //column start set_lcd_8b_reg(0x04,0x00); set_lcd_8b_reg(0x05,0xef); //column end set_lcd_8b_reg(0x06,0x00); set_lcd_8b_reg(0x07,0x00); //row start set_lcd_8b_reg(0x08,0x01); set_lcd_8b_reg(0x09,0x3f); //row end wr_8b_format(0x22); //start gram write http://www..net/ datasheet pdf - http://www..net/
-p.39- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // power off setting set_lcd_8b_reg(0x28,0x38); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); m51_wr_reg(u05_lcd_power_on, 0x00); //vci & iovcc off //################################################# ################# // enter idle mode setting set_lcd_8b_reg(0x18,0x34); //i/p_radj,n/p_radj, idl e mode 55hz set_lcd_8b_reg(0x2f,0x11); //idle mode line inversi on set_lcd_8b_reg(0x01,0x04); //idle='1' , enter idle mode // exit idle mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode line inver sion set_lcd_8b_reg(0x01,0x00); //idle='0', exit idle mo de //################################################# ################# // enter partial mode setting 32line set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj part ial mode 75hz set_lcd_8b_reg(0x2f,0x11); //partial mode line inve rsion set_lcd_8b_reg(0x01,0x01); //ptl='1', enter partial mode set_lcd_8b_reg(0x0a,0x00); //psl[15:8]=0x00 set_lcd_8b_reg(0x0b,0x20); //psl[7:0]=0x20 set_lcd_8b_reg(0x0c,0x00); //pel[15:8]=0x00 set_lcd_8b_reg(0x0d,0x47); //pel[7:0]=0x47 set_lcd_8b_reg(0x26,0x01); //refresh cycle=5frame // exit partial mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode, line inve rsion set_lcd_8b_reg(0x01,0x00); //ptl='0', exit partial mode http://www..net/ datasheet pdf - http://www..net/
-p.40- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // enter partial + idle mode setting 32line set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, par tial mode 55hz set_lcd_8b_reg(0x2f,0x11); // partial + idle mode l ine inversion set_lcd_8b_reg(0x01,0x09); // ptl='1' idle=1, ent er partial + idle mode set_lcd_8b_reg(0x0a,0x00); //psl[15:8]=0x00 set_lcd_8b_reg(0x0b,0x20); //psl[7:0]=0x20 set_lcd_8b_reg(0x0c,0x00); //pel[15:8]=0x00 set_lcd_8b_reg(0x0d,0x47); //pel[7:0]=0x47 set_lcd_8b_reg(0x26,0x01); //refresh cycle=5frame // exit partial + idle mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj ,nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode, line inve rsion set_lcd_8b_reg(0x01,0x00); // ptl='0' idle=0, exi t partial + idle mode //################################################# ################# // enter sleep mode setting set_lcd_8b_reg(0x28,0xb8); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); // exit sleep mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x80);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x90);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd0);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3c); //gon=1, dte=1, d=1100 http://www..net/ datasheet pdf - http://www..net/
-p.41- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // enter deep sleep mode setting set_lcd_8b_reg(0x28,0xb8); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); set_lcd_8b_reg(0x01,0xc0); //dp_stb[1:0]=11 // exit deep sleep mode setting set_lcd_8b_reg(0x01,0x00); //dp_stb='0', out deep s leep delayx1ms(10); set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x80);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x90);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd0);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3c); //gon=1, dte=1, d=1100 wr_8b_format(0x22); //start gram write http://www..net/ datasheet pdf - http://www..net/
-p.42- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. 1.2 cpt 1.2-1 cpt 2.0 reference fpc circuit /cs rs vci title size document number rev date: sheet of driver ic himax hx8347d a01 cpt 2.0" fpc rev a01 b 1 1 wednesday , october 08, 2008 c08 1u/10v notes 2 set ifsel="0" register-content interface mode. - vpp_otp 1 1 - c04 1u/10v notes 3 set im3~im0="1000" 80 system 18bit type i interface. notes 1 set iovcc=2.8v(1.65~3.3v);vci=2.8v(2.5~3.3v) c05 1u/10v 0 sda,scl,rs vcom /cs db4 vpp_otp vpp_otp te db1 im3 te im2 vci vci iovcc db5 db2 db3 im3 im2 vcom im1 im0 valid data bus interface 0 0 00 0 0 0 0 1 0 1 0 01 1 0 db17-10, db8-1 db7-0 db15-0 1 db17-10 id - - sda,scl 0 0 0 0 0 1 0 1 1 1 1 1 0 1 0 db17-0 iovcc vcl db17-9 db8-0 db17-0 8080 mcu 18 bits parallel c09 1u/6.3v gnd db13 db15 db16 j1 vci 1 vci 2 gnd 3 vcc 4 vcc 5 rest 6 db17 7 db16 8 db15 9 db14 10 db13 11 db12 12 db11 13 db10 14 db9 15 db8 16 db7 17 db6 18 db5 19 db4 20 db3 21 db2 22 db1 23 db0 24 rd 25 wr 26 rs 27 cs 28 flm 29 gnd 30 bl+ 31 bl- 32 db12 db17 db11 db9 /reset db14 db6 db8 /rd db7 db10 db0 /wr rs te gnd im0 3-wire serial interface 8080 mcu 8-bits parallel type ii 8080 mcu 16-bits parallel type ii 8080 mcu 18-bits parallel type ii 8080 mcu 16-bits parallel type i 8080 mcu 9-bits parallel type ii 4-wire serial interface 8080 mcu 9-bits parallel type i c01 ( c11p/n ) 8080 mcu 18-bits paralle type i 8080 mcu 8-bits parallel type i c02 ( c12p/n )(optional) recommended spec. capacitor c03 ( ddvdh ) 1uf / 6.3volt. c06 ( vgh ) c05 ( c22p/n ) c04 ( c21p/n ) c09 ( vcl) c08 ( c31p/n ) c07 ( vgl ) 1uf / 6.3volt. c10 ( vddd ) 1uf / 10 volt. 1uf / 10 volt. 1uf / 10 volt. 1uf / 6.3 volt. 1uf / 16 volt. 1uf / 25 volt. 1uf / 6.3 volt. 1uf / 6.3 volt. cog2 cog1 cabc_pwmout og1 cog1 cog2 cog2 cabc_pwmout cabc_pwmout vgh c06 1u/25v im1 vgl c07 1u/16v u1 cpt panel vcom 2 cog1 3 cog2 4 c21p 5 c21n 6 c22p 7 c22n 8 vgh 9 vgh 10 dummy 11 vgl 12 vgl 13 vtest 14 cabc_pwmout 15 vcl 16 vcl 17 c31p 18 c31p 19 c31n 20 c31n 21 vpp_otp 22 vpp_otp 23 vssd 24 vssd 25 vssc 26 vssc 27 vssc 28 vssa 29 vssa 30 vssa 31 vssa 32 vssa 33 vci 34 vci 35 dnc_scl 36 ncs 37 vsync 38 hsync 39 dotclk 40 de 41 nreset 42 nrd 43 nwr_scl 44 im3 45 im2 46 im1 47 im0 48 sda 49 db17 50 db16 51 db15 52 test9 53 db14 54 db13 55 test8 56 db12 57 db11 58 test7 59 db10 60 db9 61 test6 62 db8 63 db7 64 test5 65 db6 66 db5 67 test4 68 db4 69 db3 70 test3 71 db2 72 db1 73 db0 74 te 75 cabc_pwm_out 76 osc 77 iovcc 78 iovcc 79 vddd 80 vddd 81 vddd 82 vddd 83 vddd 84 vddd 85 c12p 86 c12p 87 c12n 88 c12n 89 c11p 90 c11p 91 c11n 92 c11n 93 ddvdh 94 vcom 1 ddvdh 95 vreg1 96 ifsel 97 vcoml_dum 98 vcomh_dum 99 rcm0 100 rcm1 101 srgb 102 smx 103 smy 104 vcom_dum 105 vcom_dum 106 ddvdh c03 1u/10v c01 1u/6.3v c02 1u/6.3v (open) vddd c10 1u/6.3v iovcc db1 db0 te db3 db4 db2 db5 db6 db10 db7 db8 db11 db12 db9 db15 db16 db13 db14 db17 im3 im0 im1 im2 /rd /wr /reset http://www..net/ datasheet pdf - http://www..net/
-p.43- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. 1.2-2 initial code for cpt 2.0 //################################################# #################. m51_wr_reg(u05_lcd_power_on, 0x0f); //vci & iovcc on delayx1ms(10); //reset m51_wr_reg(u05_lcd_rst, 0x01); // lcd hw rst ena ble delayx1ms(5); m51_wr_reg(u05_lcd_rst, 0x00); // lcd hw rst dis able. delayx1ms(10); //driving ability setting set_lcd_8b_reg(0xea,0x00); //ptba[15:8] set_lcd_8b_reg(0xeb,0x20); //ptba[7:0] set_lcd_8b_reg(0xec,0x0c); //stba[15:8] set_lcd_8b_reg(0xed,0xc4); //stba[7:0] set_lcd_8b_reg(0xe8,0xc8); //opon[7:0] set_lcd_8b_reg(0xe9,0xc8); //opon1[7:0] set_lcd_8b_reg(0xf1,0x01); //otps1b set_lcd_8b_reg(0xf2,0x10); //gen set_lcd_8b_reg(0x2e,0x86); //gdoff(70) set_lcd_8b_reg(0x29,0xff); //rtn (22) set_lcd_8b_reg(0xe4,0x01); //eq (10) set_lcd_8b_reg(0xe7,0x01); //eq (10) //gamma 2.2 setting set_lcd_8b_reg(0x40,0x00); // set_lcd_8b_reg(0x41,0x00); // set_lcd_8b_reg(0x42,0x01); // set_lcd_8b_reg(0x43,0x12); // set_lcd_8b_reg(0x44,0x10); // set_lcd_8b_reg(0x45,0x26); // set_lcd_8b_reg(0x46,0x08); // set_lcd_8b_reg(0x47,0x54); // set_lcd_8b_reg(0x48,0x02); // set_lcd_8b_reg(0x49,0x15); // set_lcd_8b_reg(0x4a,0x19); // set_lcd_8b_reg(0x4b,0x19); // set_lcd_8b_reg(0x4c,0x16); // set_lcd_8b_reg(0x50,0x19); // set_lcd_8b_reg(0x51,0x2f); // set_lcd_8b_reg(0x52,0x2d); // set_lcd_8b_reg(0x53,0x3e); // set_lcd_8b_reg(0x54,0x3f); // set_lcd_8b_reg(0x55,0x3f); // set_lcd_8b_reg(0x56,0x2b); // set_lcd_8b_reg(0x57,0x77); // set_lcd_8b_reg(0x58,0x09); // set_lcd_8b_reg(0x59,0x06); // set_lcd_8b_reg(0x5a,0x06); // set_lcd_8b_reg(0x5b,0x0a); // set_lcd_8b_reg(0x5c,0x1d); // http://www..net/ datasheet pdf - http://www..net/
-p.44- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. set_lcd_8b_reg(0x5d,0xcc); // //power voltage setting set_lcd_8b_reg(0x1b,0x16); //vrh=4.4v set_lcd_8b_reg(0x1c,0x06); //ap set_lcd_8b_reg(0x1a,0x02); //bt (vgh~15v,vgl~-10v,d dvdh~5v) set_lcd_8b_reg(0x24,0x57); //vmh(vcom high voltage ~3.85v) set_lcd_8b_reg(0x25,0x64); //vml(vcom low voltage - 1.0v) //****vcom offset**/// set_lcd_8b_reg(0x23,0x80); //for flicker adjust //c an reload from otp set_lcd_8b_reg(0x2f,0x01); //for flicker adjust //c an reload from otp //power on setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x1c,0x06); //osc_en='1', start osc set_lcd_8b_reg(0x01,0x00); //dp_stb='0', out deep s leep set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb =0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x80);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=0, st b=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x90);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=0, stb =0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd0);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=0, st b=0 delayx1ms(5); //262k/65k color selection set_lcd_8b_reg(0x17,0x06); //default 0x06 262k colo r // 0x05 65k color //set panel set_lcd_8b_reg(0x36,0x00); //ss_p, gs_p,rev_p,bgr_p //display on setting set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3c); //gon=1, dte=1, d=1100 //set gram area set_lcd_8b_reg(0x02,0x00); set_lcd_8b_reg(0x03,0x00); //column start set_lcd_8b_reg(0x04,0x00); set_lcd_8b_reg(0x05,0xef); //column end set_lcd_8b_reg(0x06,0x00); set_lcd_8b_reg(0x07,0x00); //row start set_lcd_8b_reg(0x08,0x01); set_lcd_8b_reg(0x09,0x3f); //row end wr_8b_format(0x22); //start gram write http://www..net/ datasheet pdf - http://www..net/
-p.45- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // power off setting set_lcd_8b_reg(0x28,0x38); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); m51_wr_reg(u05_lcd_power_on, 0x00); //vci & iovcc off //################################################# ################# // enter idle mode setting set_lcd_8b_reg(0x18,0x34); //i/p_radj,n/p_radj, idl e mode 55hz set_lcd_8b_reg(0x2f,0x11); //idle mode line inversi on set_lcd_8b_reg(0x01,0x04); //idle='1' , enter idle mode // exit idle mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode line inver sion set_lcd_8b_reg(0x01,0x00); //idle='0', exit idle mo de //################################################# ################# // enter partial mode setting 32line set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj part ial mode 75hz set_lcd_8b_reg(0x2f,0x11); //partial mode line inve rsion set_lcd_8b_reg(0x01,0x01); //ptl='1', enter partial mode set_lcd_8b_reg(0x0a,0x00); //psl[15:8]=0x00 set_lcd_8b_reg(0x0b,0x20); //psl[7:0]=0x20 set_lcd_8b_reg(0x0c,0x00); //pel[15:8]=0x00 set_lcd_8b_reg(0x0d,0x47); //pel[7:0]=0x47 set_lcd_8b_reg(0x26,0x01); //refresh cycle=5frame // exit partial mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode, line inve rsion set_lcd_8b_reg(0x01,0x00); //ptl='0', exit partial mode http://www..net/ datasheet pdf - http://www..net/
-p.46- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // enter partial + idle mode setting 32line set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, par tial mode 55hz set_lcd_8b_reg(0x2f,0x11); // partial + idle mode l ine inversion set_lcd_8b_reg(0x01,0x09); // ptl='1' idle=1, ent er partial + idle mode set_lcd_8b_reg(0x0a,0x00); //psl[15:8]=0x00 set_lcd_8b_reg(0x0b,0x20); //psl[7:0]=0x20 set_lcd_8b_reg(0x0c,0x00); //pel[15:8]=0x00 set_lcd_8b_reg(0x0d,0x47); //pel[7:0]=0x47 set_lcd_8b_reg(0x26,0x01); //refresh cycle=5frame // exit partial + idle mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj ,nor mal mode 75hz set_lcd_8b_reg(0x2f,0x11); //normal mode, line inve rsion set_lcd_8b_reg(0x01,0x00); // ptl='0' idle=0, exi t partial + idle mode //################################################# ################# // enter sleep mode setting set_lcd_8b_reg(0x28,0xb8); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); // exit sleep mode setting set_lcd_8b_reg(0x18,0x36); //i/p_radj,n/p_radj, nor mal mode 75hz set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x80);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x90);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd0);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3f); //gon=1, dte=1, d=1100 http://www..net/ datasheet pdf - http://www..net/
-p.47- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. //################################################# ################# // enter deep sleep mode setting set_lcd_8b_reg(0x28,0xb8); //gon=1 dte=1 d[1:0] =10 delayx1ms(40); set_lcd_8b_reg(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=1 delayx1ms(40); set_lcd_8b_reg(0x28,0x04); //gon=0 dte=0 d[1:0] =01 delayx1ms(40); set_lcd_8b_reg(0x19,0x00); //osc_en=0 delayx1ms(5); set_lcd_8b_reg(0x01,0xc0); //dp_stb[1:0]=11 // exit deep sleep mode setting set_lcd_8b_reg(0x01,0x00); //dp_stb='0', out deep s leep delayx1ms(10); set_lcd_8b_reg(0x19,0x01); //osc_en='1', start osc set_lcd_8b_reg(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x80);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0x90);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x1f,0xd0);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=0, stb=0 delayx1ms(5); set_lcd_8b_reg(0x28,0x38); //gon=1, dte=1, d=1000 delayx1ms(40); set_lcd_8b_reg(0x28,0x3f); //gon=1, dte=1, d=1100 wr_8b_format(0x22); //start gram write http://www..net/ datasheet pdf - http://www..net/
-p.48- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. 2. rgb mode reference fpc circuit capacitor c01 ( c11p/n ) c02 ( c12p/n )(optional) recommended spec. c04 ( c21p/n ) c03 ( ddvdh ) 1uf / 6.3volt. c07 ( vgl ) c06 ( vgh ) c05 ( c22p/n ) c09 ( vcl) c08 ( c31p/n ) 1uf / 10 volt. 1uf / 6.3volt. c10 ( vddd ) 1uf / 25 volt. 1uf / 10 volt. 1uf / 10 volt. 1uf / 6.3 volt. 1uf / 16 volt. 1uf / 6.3 volt. 1uf / 6.3 volt. rcm0 vcoml vcomh rcm1 cabcpwm cabcpwm vreg1 srgb="0" s1,s2,s3="b,g,r" smy="0" g1->g320 smx="0" s720->s1 c3 ddvdh vtest c11n c11p c12p c12n vsync de dotclk hsync hsy nc hsy nc enable enable dotclk dotclk vsy nc vsy nc rcm0 rcm1 dotclk conn2 conn2 nreset dnc_scl 2. sdi pin is i/o pin. sdo is no use. 3. the input pin must be fixed iovcc or gnd when no use. refer to "pin description". ddvdh vcl ncs vreg1 vgh vgl vcom vcoml vddd vcomh c31p c31n c8 c31n c31p vcom2 vcom ncs2 ncs c22p vddd2 vddd dnc_scl1 dnc_scl1 ddvdh2 ddvdh vcomh2 vcomh c12n c12p c2 (open) vgh nreset 240rgb x 320 tft panel c11p c1 c11n c10 vcoml2 vcoml db8 vcl2 vcl db9 db7 nreset2 nreset db10 vgl2 vgl vddd db12 db11 db13 db14 iovcc db17 db16 db15 iovcc sda te nreset vci vreg2 vreg1 vgh2 vgh gnd db1 db0 db3 db2 db6 db5 db4 c9 c22n iovcc vci hsync vsync c6 de vpp_otp vssd vssa vssc c7 vcl vgl c21n c21p c4 c5 ncs c22p c22n c21n c21p gnd sda vtest2 vtest ncs vssa gnd vssd vssc gnd3 gnd gnd4 gnd j2 fpc60-0.5-4.0l vci 1 vci 2 gnd 3 vcc 4 iovcc 5 nreset 6 db17 13 db16 14 db15 15 db14 16 db13 17 db12 18 db11 19 db10 20 db9 21 db8 22 db7 23 db6 24 db5 25 db4 26 db3 27 db2 28 db1 29 db0 30 nrd_e 31 nwr_rnw 32 dnc 33 ncs 34 flm 35 gnd 36 pwm_out 37 vsync 38 hsync 39 dotclk 40 enable 41 sdo 42 sdi 43 nc 44 shut 45 rl 46 tb 47 idm 48 rev 49 rcm0 50 rcm1 51 extc 52 dbs 53 im3 54 im2 55 im1 56 im0 57 gnd 58 bl+/nc 59 bl_gnd/nc 60 db23 7 db22 8 db21 9 db20 10 db19 11 db18 12 1. vci, iovcc are separated from different power so urce to get better display quality. vci iovcc iovcc2 iovcc vci2 vci vtest db11 db5 db15 db13 db10 db8 db9 db12 db14 db3 db4 db7 db2 db0 db6 db16 db1 nwr_scl db17 vsync rcm[1:0]="11" rgb mode2 (hs+vs) rcm[1:0]="10" rgb mode1 (hs+vs+de) hsync nwr_scl dotclk ifsel="0" register-content interface u2 HX8347-D (bump up) vgl c11p vpp_otp hsync dotclk de nreset nrd_e nwr_rnw im3 im2 c22n ddvdh c22p g2 g4 g320 g1 g3 g317 g319 s1 s2 s3 s720 s719 s718 g6 g318 g315 g5 vgh c11n conn conn vcom ncs vssa dnc_scl vssc vci vssd vsync dummy27 dummy dummy23 dummy24 s262 s263 s361 s265 s266 s267 c21p c21n im0 sda d17 test10 d16 d15 test9 d14 d13 test8 d12 d11 test7 d10 d9 test6 d8 d7 test5 d6 d5 test4 d4 d3 test3 d2 d1 d0 test2 te cabc_pwm_out osc iovcc vddd c12p c12n c31p c31n vcl vreg1 vtest vmoni vcomh_dummy vcoml_dummy rcm1 rcm0 srgb smx smy ifsel vcom_dummy im1 test1 cabcpwmout de conn1 conn3 conn1 conn2 conn4 conn2 cabcpwm pwm1 pwm vpp_otp2 vpp_otp vpp_otp figure 2. 1 the HX8347-D spi+rgb application refere nce circuit http://www..net/ datasheet pdf - http://www..net/
-p.49- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. 2.1. initial code for reference //for cmo 2.6 //################################################# ################# m51_wr_reg(u13_rgb_if_enable, 0x13); // rgb if timing enable. delayx1ms(5); //reset m51_wr_reg(u05_lcd_rst, 0x01); // lcd hw rst ena ble delayx1ms(5); m51_wr_reg(u05_lcd_rst, 0x00); // lcd hw rst dis able. delayx1ms(10); //driving ability setting set_lcd_spi_reg_8b(0xea,0x00); //ptba[15:8] set_lcd_spi_reg_8b(0xeb,0x20); //ptba[7:0] set_lcd_spi_reg_8b(0xec,0x0c); //stba[15:8] set_lcd_spi_reg_8b(0xed,0xc4); //stba[7:0] set_lcd_spi_reg_8b(0xe8,0x38); //opon[7:0] set_lcd_spi_reg_8b(0xe9,0x10); //opon1[7:0] set_lcd_spi_reg_8b(0xf1,0x01); //otps1b set_lcd_spi_reg_8b(0xf2,0x10); //gen //gamma 2.2 setting set_lcd_spi_reg_8b(0x40,0x01); // set_lcd_spi_reg_8b(0x41,0x00); // set_lcd_spi_reg_8b(0x42,0x00); // set_lcd_spi_reg_8b(0x43,0x10); // set_lcd_spi_reg_8b(0x44,0x0e); // set_lcd_spi_reg_8b(0x45,0x24); // set_lcd_spi_reg_8b(0x46,0x04); // set_lcd_spi_reg_8b(0x47,0x50); // set_lcd_spi_reg_8b(0x48,0x02); // set_lcd_spi_reg_8b(0x49,0x13); // set_lcd_spi_reg_8b(0x4a,0x19); // set_lcd_spi_reg_8b(0x4b,0x19); // set_lcd_spi_reg_8b(0x4c,0x16); // set_lcd_spi_reg_8b(0x50,0x1b); // set_lcd_spi_reg_8b(0x51,0x31); // set_lcd_spi_reg_8b(0x52,0x2f); // set_lcd_spi_reg_8b(0x53,0x3f); // set_lcd_spi_reg_8b(0x54,0x3f); // set_lcd_spi_reg_8b(0x55,0x3e); // set_lcd_spi_reg_8b(0x56,0x2f); // set_lcd_spi_reg_8b(0x57,0x7b); // set_lcd_spi_reg_8b(0x58,0x09); // set_lcd_spi_reg_8b(0x59,0x06); // set_lcd_spi_reg_8b(0x5a,0x06); // set_lcd_spi_reg_8b(0x5b,0x0c); // set_lcd_spi_reg_8b(0x5c,0x1d); // set_lcd_spi_reg_8b(0x5d,0xcc); // //power voltage setting set_lcd_spi_reg_8b(0x1b,0x1b); //vrh=4.65v set_lcd_spi_reg_8b(0x1a,0x01); //bt (vgh~15v,vgl~-1 0v,ddvdh~5v) http://www..net/ datasheet pdf - http://www..net/
-p.50- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. set_lcd_spi_reg_8b(0x24,0x2f); //vmh(vcom high volt age ~3.2v) set_lcd_spi_reg_8b(0x25,0x57); //vml(vcom low volta ge -1.2v) //****vcom offset**/// set_lcd_spi_reg_8b(0x23,0x88); //for flicker adjust //can reload from otp //power on setting set_lcd_spi_reg_8b(0x19,0x01); //osc_en='1', start osc set_lcd_spi_reg_8b(0x01,0x00); //dp_stb='0', out de ep sleep set_lcd_spi_reg_8b(0x1f,0x88);// gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_spi_reg_8b(0x1f,0x80);// gas=1, vomg=00, pon=0, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_spi_reg_8b(0x1f,0x90);// gas=1, vomg=00, pon=1, dk=0, xdk=0, dvdh_tri=0, stb=0 delayx1ms(5); set_lcd_spi_reg_8b(0x1f,0xd0);// gas=1, vomg=10, pon=1, dk=0, xdk=0, ddvdh_tri=0, stb=0 delayx1ms(5); //262k/65k color selection set_lcd_spi_reg_8b(0x17,0x60); //default 0x60 262k color // 0x50 65k color //display on setting set_lcd_spi_reg_8b(0x28,0x38); //gon=1, dte=1, d= 1000 delayx1ms(40); set_lcd_spi_reg_8b(0x28,0x3f); //gon=1, dte=1, d= 1100 //set window area set_lcd_spi_reg_8b(0x02,0x00); set_lcd_spi_reg_8b(0x03,0x00); //column start set_lcd_spi_reg_8b(0x04,0x00); set_lcd_spi_reg_8b(0x05,0xef); //column end set_lcd_spi_reg_8b(0x06,0x00); set_lcd_spi_reg_8b(0x07,0x00); //row start set_lcd_spi_reg_8b(0x08,0x01); set_lcd_spi_reg_8b(0x09,0x3f); //row end //################################################# ################# // power off setting set_lcd_spi_reg_8b(0x28,0x38); //gon=1 dte=1 d[ 1:0]=10 delayx1ms(40); set_lcd_spi_reg_8b(0x1f,0x89); // gas=1, vomg=00, pon=0, dk=1, xdk=0, dvdh_tri=0, stb =1 delayx1ms(40); set_lcd_spi_reg_8b(0x28,0x04); //gon=0 dte=0 d[ 1:0]=01 delayx1ms(40); set_lcd_spi_reg_8b(0x19,0x00); //osc_en=0 delayx1ms(5); m51_wr_reg(u05_lcd_power_on, 0x00); //vci & iovcc off http://www..net/ datasheet pdf - http://www..net/
-p.51- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. 3. otp programming ya[2:0]=11 1 ya[2:0]=11 0 ya[2:0]=1 01 ya[2:0]=1 00 ya[2:0]=0 11 ya[2:0]=0 10 ya[2:0]=0 01 ya[2:0]=0 00 non-progr am xa[4:0]=00h id17 id16 id15 id14 id13 id12 id11 id10 00h xa[4:0]=01h valid_id id26 id25 id24 id23 id22 id21 id20 00h xa[4:0]=02h id37 id36 id35 id34 id33 id32 id31 id30 00h xa[4:0]=03h vmf17 vmf16 vmf15 vmf14 vmf13 vmf12 vmf11 vmf10 00h xa[4:0]=04h vmf27 vmf26 vmf25 vmf24 vmf23 vmf22 vmf21 vmf20 00h xa[4:0]=05h vmf37 vmf36 vmf35 vmf34 vmf33 vmf32 vmf31 vmf30 00h xa[4:0]=06h vmh7 vmh6 vmh5 vmh4 vmh3 vmh2 vmh1 vmh0 00h xa[4:0]=07h vml7 vml6 vml5 vml4 vml3 vml2 vml1 vml0 00h xa[4:0]=08h -- -- -- valid_vm l valid_vm h valid_vmf 3 valid_vmf 2 valid_vmf 1 00h xa[4:0]=09h valid_pane l ddvdh_t ri ss_panel gs_pane l rev_pan el bgr_pan el 00h table 3. 1 otp address mapping note: valid bit must program if user want use this otp function find optimized value and record them (only 1 needs to be programmed) set otp_otpen=1 (r38h=14h) set otp_pprog=1 (r38h=16h) apply external voltage to vpp 6.5v set related address to xa[4:0] & ya[2:0] set otp_pwe=1 (r38h=17h) set otp_pwe=0 (r38h=16h) floating external voltage 6.5v set otp_pprog=0 (r38h=04h) set otp_otpen=0 (r38h=00h) re-power on wait> 600us wait >1us wait >1us wait 1us wait >1us wait 1us wait 1us wait 1us wait 1us http://www..net/ datasheet pdf - http://www..net/
-p.52- himax confidential sep, 2008 HX8347-D(t) 240rgb x 320 dot, 262k color, tft mobile single chi p driver application note preliminary v01 this information contained herein is the exclusive property of himax and shall not be distributed, rep roduced, or disclosed in whole or in part without prior written permissio n of himax. 4. revision history version date description of changes 2008/08/11 new setup 2008/08/20 p7 and p13 modify vcom setting 2008/09/15 modify p11 spi+rgb reference fpc circuit modify normal mode at 70hz modify p14 otp programming 2008/10/13 add cmo 2.0 application 2008/10/17 1. modify p8 p9 p10 cmo2.6 power off se tting, enter sleep mode setting, and enter deep sleep mode setting 2. modify p14 p15 p16 cmo2.0 power off setting, enter sleep mode setting, and enter deep sleep mode setting 2008/11/12 modify cmo 2.0 application circuit 2008/11/14 add cmo 2.2 and 2.8 initial code 2009/03/04 add cmo 2.4 initial code 2009/03/18 add cpt2.0 application add id otp table 01 2009/05/25 add cmo 2223 panel initial code add cmo 2807 panel initial code http://www..net/ datasheet pdf - http://www..net/

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